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Boundary Scan |
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Software |
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Introduction
> Hardware
> Software
> Software
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Acculogic's
new integrated Boundary Scan Test and Programming Environment consists of
test
programming and run-time modules that utilize Microsoft's .NET technology and XML to ease
project management, increase productivity and potentially allow full integration of test
data, programming information and diagnostic databases with third
party testability and
coverage analysis tools.
The new IDE provides a fully unified and integrated development and run time environment
for all Boundary Scan test and programming applications. Now you can develop
Interconnect/Structural test, cluster functional test, memory test and flash programming
routines quickly and using common set of tools. ScanTracer, Acculogic's powerful graphical
Boundary Scan Logic Analyzer provides pattern debugging and DiagViewer links schematic and
layout with diagnostics. |
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Access Analyzer (AA) automates pre-layout testability analysis
AA tools are typically used after schematic capture and before CAD
layout for assemblies
that have a mix of scan and non-scan devices. AA generates two reports to help design and
test engineers make the most effective use of physical and virtual access to the
assembly-under-test.
The Virtual Interconnect Test (VIT) report identifies all the pure scan nets and scan
control nets (TDI/TDO interconnects) that can be fully tested by VIT and TAPIT techniques
and where physical test points can be eliminated without jeopardizing test coverage. The
Virtual Component Test report identifies the nets where adding physical access will permit
VCCT testing of non-scan devices. |
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Virtual Interconnect Test (VIT) offers 100% pin-level fault
coverage
The VIT module generates patterns to test boundary scan nets using only the virtual access
provided by the Boundary Scan (JTAG) circuitry.
On pure boundary scan nets, VIT verifies that every device is operational at the pin level
and that every interconnect - from silicon to lead bonds, from solder bonds to the circuit
board itself - is intact.
VIT patterns are generated automatically from a circuit netlist and the BSDL models of
boundary scan devices. |
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Virtual Component/Cluster Test (VCCT) extends access to non-scan
circuitry
The VCCT module uses boundary scan access to detect open and stuck-at fault on the leads
of non-scan devices, eliminating the need for physical access to the signal pins of those
devices. VCCT can be used to test either a single or a cluster of non-scan components.
VCCT uses the scan cells of boundary scan devices as virtual ATE channels to drive
stimulus to and detect response from non-scan logic devices. VCCT can also use a
combination of virtual channels and real ATE channels for driving and detecting.
Stimulus patterns are conventional parallel test patterns, which VCCT regenerates in a
serial format to apply via the boundary scan path. Patterns for component test may be
available from an in-circuit test library, a design pattern library, or they may have to
be generated manually. Cluster test patterns are usually generated manually, often with
the help of a logic simulator. |
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Boundary Function Test (BFT) finds faults in internal device logic
The BFT module uses the optional built-in test features available on some boundary scan
devices to test internal device logic as part of an assembly or board-level test.
BFT is an effective toolset for manufacturers who retest internal device logic as part of
the assembly process and for repair depots responsible for isolating failures in the
field.
Support four techniques for internal testing of 1149.1 devices:
- Functional test of the device TAP and scan register circuitry.
- Device logic test using the 1149.1 INTEST instruction
- Device logic test using the internal scan technology
- Device logic test using the 1149.1 RUN BIST instruction |
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Memory Test Pattern Generator
Even though memory devices such as RAMs do not currently support IEEE 1149.1, processors,
ASIC's, FPGAs and other programmable parts that often control them do.
The control devices for which JTAG standard is implemented can
provide access to the bus
through their JTAG port, therfore facilitating on-board memory testing. |
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MemTest
MemTest is a powerful and easy to use software tool that the test and design engineers can
take advantage of to automatically develop routines to test the RAM banks on the DUT.
Combined with the high throughput of ScanMaster controllers, every memory location can be
tested quickly using different test algorithms that are supported by
MemTest. |
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Boundary Scan Intelligent Diagnostics (BSID)
quickly isolates faults
BSID generates clear diagnostic infromation for the following failure categories:-
- TAP circuitry and chain failures detected by TAPIT
- Net failures detected by VIT
- Device or cluster failures detected by VCCT
When a boundary scan test fails, BSID uses the failure data generated by this module and
compares it with actual test results to isolate the failing devices and nets. To generate
diagnostics for a virtual cluster test, BSID can use fault-dictionary techniques if a
fault-dictionary database is supplied. BSID quickly isolates common faults such as shorts,
opens and stuck-at pins, as well as difficult-to-detect strong driver shorts and bus
faults. |
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Click here for more spec
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